The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of the IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC manufacturing are needed.
For example, as the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design have resulted in the development of multilayer integrated devices that have varying or high topography. For example, devices that have varying or high topography include field effect transistor (FET) devices and fin-like field effect transistor (Fin-FET) devices. The fabrication processes for forming FET and Fin-FET devices includes forming photoresist layers to define various device areas or regions. However, in certain situations, forming the photoresist layers has proved difficult. Accordingly, although existing methods of fabricating devices with varying or high topography have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.